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Signals/Connections
Table 2-12. Enhanced Synchronous Serial Interface 1 (ESSI1) (Continued)
Signal
Name
SCK1
Type
Input/Output
State During
Reset 1, 2
Ignored input
Serial Clock
Signal Description
Provides the serial bit rate clock for the ESSI interface for both the transmitter
and receiver in Synchronous modes, or the transmitter only in Asynchronous
modes.
Although an external serial clock can be independent of and asynchronous to
the DSP system clock, it must exceed the minimum clock cycle time of 6 T
(that is, the system clock frequency must be at least three times the external
ESSI clock frequency). The ESSI needs at least three DSP phases inside
each half of the serial clock.
PD3
Input or Output
Port D 3
The default configuration following reset is GPIO. For PD3, signal direction is
controlled through PRRD.
This signal is configured as SCK1 or PD3 through PCRD. This input is 5 V
tolerant.
SRD1
Input
Ignored input
Serial Receive Data
Receives serial data and transfers the data to the ESSI receive shift register.
SRD0 is an input when data is being received.
PD4
Input or Output
Port D 4
The default configuration following reset is GPIO. For PD4, signal direction is
controlled through PRRD. This signal is configured as SRD1 or PD4 through
PCRD. This input is 5 V tolerant.
STD1
Output
Ignored input
Serial Transmit Data
Transmits data from the serial transmit shift register. STD1 is an output when
data is being transmitted.
PD5
Input or Output
Port C 5
The default configuration following reset is GPIO. For PD5, signal direction is
controlled through PRRD. This signal is configured as STD1 or PD5 through
PCRD. This input is 5 V tolerant.
Notes: 1.
2.
2-16
In the Stop state, the signal maintains the last state as follows:
? If the last state is input, the signal is an ignored input.
? If the last state is output, these lines are tri-stated.
The Wait processing state does not affect the signal state.
DSP56311 User’s Manual, Rev. 2
Freescale Semiconductor
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